1. Field of the Invention
The present invention relates to integrated circuit design. More specifically, the present invention relates to an apparatus and a method for asynchronously controlling the transfer of data items from a sender to a receiver across a long signal line within an integrated circuit.
2. Related Art
As integrated circuit technologies produce progressively finer on-chip structures, the resistance of on-chip wires continues to grow. This trend dramatically increases the delay of long-haul wires relative to the delay of gates, hence making communication over long wires very expensive.
Circuit designers can mitigate this effect by inserting repeaters along a wire, so that data sent down the wire will be periodically “boosted” to increase transmission speed. While this well-known technique reduces delay, it does not easily improve bandwidth, since each repeater only amplifies and does not hold information.
Inserting latched repeaters along a wire can both improve delay and bandwidth, since each repeater can now also store information. But latched repeaters require a fast clock. Generating such a fast clock can be difficult and expensive. Designers, therefore, are considering moving towards asynchronous communication on long wires. With asynchronous communication, the elements on the long wires clock themselves.
FIG. 1 illustrates an asynchronous communication system that includes sending control stage 102, receiving control stage 104, sending data latch 106, and receiving data latch 108. In FIG. 1, control stage 102 is a sending control stage and control stage 104 is a receiving control stage. For the next wire to the right, stage 104 is a sending control stage.
Sending control stage 102 and receiving control stage 104 are coupled together through request line 112 and acknowledge line 110. Sending data latch 106 is coupled to receiving data latch 108 through data path 114. Note that data path 114 can include a plurality of data lines, each with its own sending data latch and receiving data latch.
The control stages 102 and 104 have inputs marked with triangles, and outputs, which have no triangles. A control stage will transmit a signal on each of its outputs only when all of its inputs have received a signal. The triangles on data latches 106 and 114 indicate clock signal inputs.
During operation, when data is available in sending data latch 106 and the first channel is available, sending control stage 102 sends a request signal on request line 112 and simultaneously causes sending data latch 106 to send a data item on data path 114. After a transit time, the request signal and the data item arrive at receiving control stage 104 and receiving data latch 108, respectively.
In response to the request signal, if the following channel is available, receiving control stage 104 causes the data to be latched into receiving data latch 108 and simultaneously sends an acknowledge signal on acknowledge line 110. After an additional transit time, the acknowledge signal arrives at sending control stage 102. When the acknowledge signal arrives at sending control stage 102, these steps can be repeated to send a subsequent data item from sending data latch 106 to receiving data latch 108.
A major drawback to this technique is that while the acknowledge signal is in-flight, data path 114 is idle. Thus, data path 114 is busy at most half of the time, and is hence significantly underutilized. Note that underutilization of data lines is a significant problem because it represents a bandwidth penalty of fifty percent. That is, without this underutilization, the datapath bandwidth could be twice as large.
Hence, what is needed is an apparatus and a method for asynchronous control of long wires without the problems described above.